1. Field of the Invention
The present invention relates to a non-volatile semiconductor storage device, and more particularly to a three-dimensional non-volatile semiconductor storage device including a charge storage layer.
2. Description of the Related Art
High integration and increased packing density of a semiconductor device have been realized based on a reduction in a minimum feature size. In a non-volatile semiconductor storage device, further continuously advancing a cell size of a memory cell based on a reduction in a minimum feature size is gradually becoming difficult due to restrictions imposed on its manufacturing processes and device designs. One of measures which solve this difficulty in miniaturization is realizing a three-dimensional semiconductor device.
An example of the three-dimensional non-volatile semiconductor storage device is disclosed in a specification of U.S. Pat. No. 6,888,750. The non-volatile semiconductor storage device has a structure where a plurality of layers of silicon-on-insulator (SOI) type memory cell arrays of non-volatile semiconductor storage devices and a plurality of interlevel insulator layers are simply laminated one another. Each memory cell array includes a plurality of stripe-like bit lines formed on the interlevel insulator, gate stacks arranged in a two-dimensional matrix each including a charge storage layer and a control gate electrode, and word lines which are provided on the control gate electrodes and connect the control gate electrodes in a direction vertical to the bit line direction. That is, the bit lines, the gate stacks, and the word lines are configured as the single layer of the memory cell array which is covered with the interlevel insulator, and the plurality of layers of memory cell arrays are laminated.
Another example of a three-dimensional semiconductor device having different structure is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2004-265975. The three-dimensional semiconductor device uses a bonding technology. According to this technology, a first semiconductor device is formed on a first SOI substrate, and is covered with an interlevel insulator to be planarized. The interlevel insulator is bonded to a second SOI substrate, a first support substrate of the first SOI layer is removed to leave a very thin semiconductor layer near a surface of the support substrate, and a second semiconductor device and/or an interconnection line are formed on the remained thin semiconductor layer.